VERA:Testbenches and Test Cases for Complex Designs

Designed for SYNOPSYS
by Si-Concepts
Free TCP/IP Packet Generator
Source Code in OpenVeraTM
with Built in Coverage Tracker

Download now!
2004 Tutorial
Mar 1, 2004 8:00-12:00 PM

Tutorial 1 • Architecting Coverage Based Verification Flows

Presenter: Ahmed Shahid
SiConcepts, Fremont, CA

Which of the following would you like to learn
Advanced RTL Design
Vera
System Verilog
System Verilog Assertions
Sugar

Member
Synopsys SystemVerilog Catalyst Program
Useful Links
Terms & Conditions
Course Catalog
Registration
FAQs
Si-Concepts Mission

To deliver world-class vera & vcs based design verification training focused on silicon based designs
Google